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234 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 12345678901 2 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 ps8164b 03/15/99 pi6c104 spread spectrum clock synthesizer for desktop pentium ii pciclk_f/s1 pciclk1 v ss pciclk3 pciclk4 pciclk2 pciclk5 pciclk6/pd# v dd 48m/mode 24m/ref/s2 v ss v dd v dd2 v dd2 cpuclk0 cpuclk1 v dd v ss sdata sclk s0 v ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 xtal_in xtal_out v dd apic ref1/p14 pin configuration block diagram features up to 112 mhz operation spread spectrum modulation for cpuclk, and pciclk two copies of cpu clock with v dd of 2.5v 5% seven copies of pci clock, (synchronous with cpu clock) 3.3v one copy of ref. clock @ 14.31818mhz (3.3v ttl ) 48mhz usb clock, 24mhz super i/o clock i 2 c serial configuration interface low cost 14.31818mhz crystal oscillator input power management control isolated core v dd , v ss pins for noise reduction 28-pin ssop (h) and soic package (s) description the pi6c104 is a high-speed low-noise clock generator designed to work with the pi6c18x family of clock buffer to meet all clock needs for desktop intel architecture platforms. cpu and chipset clock frequencies from 66.6 mhz to 112 mhz are supported. split supplies of 3.3v and 2.5v are used. the 3.3v power supply powers a portion of the i/o and the core. the 2.5v is used to power the remaining outputs (cpu and apic). 2.5v signaling follows jedec standard 8-x. power sequencing of the 3.3v and 2.5v supplies is not required. an asynchronous pd# signal may be used to orderly power down (or up) the system during power on. 28-pin h, s ref1 apic v ddref v ddapic pciclk[1:6] cpuclk[0:1] ref osc v ddcpu 2 6 v ddpci 0,1 pciclk_f div pll1 sel xtal_out xtal_in s[0..2] s data sclock i 2 c pll2 v ddp 2 pi4 48mhz 24mhz/ref mux
235 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 12345678901 2 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 ps8164b 03/15/99 pi6c104 spread spectrum clock synthesizer for desktop pentium ii pin description n i pe m a n l a n g i se p y t. y t qn o i t p i r c s e d 1n i _ l a t xi x1 t u p n i l a t s y r c z h m 8 1 3 . 4 1 2t u o _ l a t xo x1 t u p n i l a t s y r c z h m 8 1 3 . 4 1 4 f _ k l c i c po1 . t u p t u o k c o l c i c p g n i n n u r e e r f 1 su p + i1 t i b t c e l e s y c n e u q e r f e s i w r e h t o t u p t u o f _ k l c i c p , t u p n i 1 s s i n i p s i h t p u r e w o p g n i r u d 0 1 , 8 , 7 , 6 , 5] 5 : 1 [ k l c i c po5 . s t u p t u o k c o l c i c p 1 1 6 k l c i c po 1 . s t u p t u o k c o l c i c p # d pu p + i n e h w d e l b a s i d e r a s k c o l c u p c d n a i c p . t u p n i n w o d r e w o p w o l e v i t c a f _ k l c i c p r o f t p e c x e , w o l s i # d p , t u p n i # d p : 0 = e d o m . ) 3 1 n i p ( e d o m y b t e s s i n i p s i h t t u p t u o 6 k l c i c p : 1 = e d o m 3 1 m 8 4o 1 t u p t u o z h m 8 4 e d o mu p + i t u p t u o 6 k l c i c p = 1 , t u p n i # d p = 0 , 1 1 n i p f o n o i t i n i f e d e h t s e n i m r e t e d e d o m p u r e w o p r e t f a t u p t u o z h m 8 4 s e m o c e b . p u r e w o p g n i r u d d e l p m a s , t u p n i n a a s i s i h t 4 1 m 4 2o 1 t u p t u o z h m 4 2 f e ro . t u p t u o e c n e r e f e r d e r e f f u b 2 su p + i. 2 t i b t c e l e s y c n e u q e r f : s t c e l e s e d o m ) 7 2 n i p ( 4 1 p . e s i w r e h t o t u p t u o , t u p n i 2 s s i n i p s i h t p u r e w o p g n i r u d z h m 4 2 = 1 , f e r = 0 6 10 su p + i1 0 t i b t c e l e s y c n e u q e r f 7 1k l c su p + i1 i r o f k c o l c l a i r e s 2 e c a f r e t n i c 8 1a t a d su p + o i1 i r o f a t a d l a i r e s 2 e c a f r e t n i c 2 2 , 1 2] 1 : 0 [ k l c u p co2 t u p t u o k c o l c u p c 4 2c i p ao1 . t u p t u o l a t s y r c d e r e f f u b 7 2 1 f e ro1 . t u p t u o l a t s y r c d e r e f f u b 4 1 p11 z h m 4 2 = 1 , 1 f e r = 0 , t c e l e s e d o m 4 1 n i p . e s i w r e h t o t u p t u o 1 f e r , t u p n i 4 1 p s i n i p s i h t p u r e w o p g n i r u d 6 2 , 0 2 , 2 1 , 9v d d 4v 3 . 3 . l l p , f e r , e r o c , i c p r o f y l p p u s r e w o p 5 2 , 3 2v 2 d d 2v 5 . 2 . s k c o l c u p c & c i p a r o f y l p p u s r e w o p 8 2 , 9 1 , 5 1 , 3v s s 4s d n u o r g
236 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 12345678901 2 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 ps8164b 03/15/99 pi6c104 spread spectrum clock synthesizer for desktop pentium ii pi6c104 i 2 c address assignment 0d2h 2-wire i 2 c control the i 2 c interface permits individual enable/disable of each clock output and test mode enable. the pi6c104 is a slave receiver device. it can not be read back. sub addressing is not supported. all preceding bytes must be sent in order to change one of the control bytes. every byte put on the sdata line must be 8-bits long (msb first), followed by an acknowledge bit generated by the receiving device. during normal data transfers sdata changes only when sclk is low. exceptions: a high to low transition on sdata while sclk is high indicates a ?start? condition. a low to high transition on sdata while sclk is high is a ?stop? condition and indicates the end of a data transfer cycle. each data transfer is initiated with a start condition and ended with a stop condition. the first byte after a start condition is always a 7-bit address byte followed by a read/write bit. (high = read from addressed device, low = write to addressed device). if the device?s own address is detected, pi6c104 generates an acknowledge by pulling sdata line low during ninth clock pulse, then accepts the following data bytes until another start or stop condition is detected. following acknowledgement of the address byte (d2), two more bytes must be sent: 1. ?command code? byte, and 2. ?byte count? byte. although the data bits on these two bytes are ?don?t care,? they must be sent and acknowledged. 7 a6 a5 a4 a3 a2 a1 a0 a 11010010 clock enable configuration # d p] 1 : 0 [ k l c u p c] 5 : 1 [ k l c i c pf _ k l c i c ps k c o l c r e h t ol a t s y r cs ' o c v 0w o lw o lg n i n n u rg n i n n u rg n i n n u rg n i n n u r 1g n i n n u rg n i n n u rg n i n n u rg n i n n u rg n i n n u rg n i n n u r e l b a t y c n e u q e r f 0 s1 s2 su p ci c p 000 5 70 3 00 1 8 . 6 64 . 3 3 010 6 . 6 63 . 3 3 011 8 . 6 64 . 3 3 10 0 2 1 13 . 7 3 10 1 3 . 3 83 . 3 3 110 0 0 13 . 3 3 111 0 0 13 . 3 3
237 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 12345678901 2 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 ps8164b 03/15/99 pi6c104 spread spectrum clock synthesizer for desktop pentium ii byte 3 : frequency, spread spectrum byte 4 : clock controls (1 = enabled, 0 = disabled) # t i bp u p# n i pe m a nn o i t p i r c s e d 7 0 ~d v s rd e v r e s e r 6~0 s0 t i b t c e l e s y c n e u q e r f 5~1 s1 t i b t c e l e s y c n e u q e r f 4~2 s2 t i b t c e l e s y c n e u q e r f 3~s f s t c e l e s y c n e u q e r f e r a w d r a h = 0 1 ( t c e l e s y c n e u q e r f e r a w t f o s = 1 2 ) . g e r c 2~d v s rd e v r e s e r 1~1 e d o m1 t i b e d o m 0~0 e d o m0 t i b e d o m 1 m0 m 00 f f o m u r t c e p s d a e r p s 01 e d o m t s e t 10 n o m u r t c e p s d a e r p s 11 z - i h byte 5 : pci clock control (1 = enabled, 0 = disabled) # t i bp u p# n i pe m a nn o i t p i r c s e d 7 0 ~ d v s rd e v r e s e r 6~ 5~ 4~ 3~ 21 1 2n e 1 u p ce l b a n e s i t l u a f e d , e l b a n e 1 k l c u p c 10~ d v s rd e v r e s e r 01 2 2n e 0 u p ce l b a n e s i t l u a f e d , e l b a n e 0 k l c u p c # t i bp u p# n i pe m a nn o i t p i r c s e d 714 n e f i c pe l b a n e s i t l u a f e d , e l b a n e f _ i c p 60 1 1n e 6 i c pe l b a n e s i t l u a f e d , e l b a n e 6 i c p 51 0 1n e 5 i c pe l b a n e s i t l u a f e d , e l b a n e 5 i c p 40~ ~ d e v r e s e r 3 1 8n e 4 i c pe l b a n e s i t l u a f e d , e l b a n e 4 i c p 27n e 3 i c pe l b a n e s i t l u a f e d , e l b a n e 3 i c p 16n e 2 i c pe l b a n e s i t l u a f e d , e l b a n e 2 i c p 05n e 1 i c pe l b a n e s i t l u a f e d , e l b a n e 1 i c p
238 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 12345678901 2 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 ps8164b 03/15/99 pi6c104 spread spectrum clock synthesizer for desktop pentium ii table 1: byte 3 frequency and spread spectrum table byte 0: test mode table s f s 3 t i bn e s s 1 t i b0 s 6 t i b1 s 5 t i b2 s 4 t i b) z h m ( u p c) z h m ( i c p) % ( d a e r p s 10000 5 70 3f f o 10001 8 . 6 64 . 3 3f f o 10010 6 . 6 63 . 3 3f f o 10011 8 . 6 64 . 3 3f f o 10100 2 1 13 . 7 3f f o 10101 3 . 3 83 . 3 3f f o 10110 0 0 13 . 3 3f f o 10111 0 0 13 . 3 3f f o 110005 70 35 . 0 + ~ 5 . 0 - 11001 8 . 6 64 . 3 39 . 0 + ~ 9 . 0 - 11010 6 . 6 63 . 7 30 . 0 + ~ 0 . 1 - 11011 8 . 6 64 . 3 35 . 0 + ~ 5 . 0 - 11100 2 1 13 . 7 35 . 0 + ~ 5 . 0 - 11101 3 . 3 83 . 3 35 . 0 + ~ 5 . 0 - 11110 0 0 13 . 3 30 . 0 + ~ 1 - 11111 0 0 13 . 3 30 . 0 + ~ 5 . 0 - 1 t i b0 t i bu p ci c pm 8 4m 4 2c i p a / f e re d o m 00 1 e l b a t1 e l b a tz h m 8 4f e r / z h m 4 2z h m 8 1 3 . 4 1l a m r o n 01 2 / n i x6 / n i x2 / n i x4 / n i xn i xt s e t 10 1 e l b a t1 e l b a tz h m 8 4f e r / z h m 4 2z h m 8 1 3 . 4 1c s s 11 z - i hz - i hz - i hz - i hz - i he t a t s - i r t byte 6 : ref clock control (1 = enabled, 0 = disabled) # t i bp u p# n i pe m a nn o i t p i r c s e d 7 0 ~d v s rd e v r e s e r 6~d v s rd e v r e s e r 54 2n e c i p ae l b a n e s i t l u a f e d , e l b a n e c i p a 4~d v s rd e v r e s e r 2 1 ~d v s rd e v r e s e r 16 21 n e f r1 e l b a n e e v i r d h g i h 1 f e r 06 20 n e f r0 e l b a n e e v i r d h g i h 1 f e r 0 n e f r 1 n e f r 0 0 e v i r d w o l1 0 t l u a f e d , e v i r d l a m r o n0 1 e v i r d h g i h1 1 note: outputs are disabled @ low state notes: bit 3 = enable software frequency select bit 1 = enable software frequency select bit 6 = frequency select 0 bit 5 = frequency select 1 bit 4 = frequency select 0
239 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 12345678901 2 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 ps8164b 03/15/99 pi6c104 spread spectrum clock synthesizer for desktop pentium ii note: 1. please note that all clocks can also be individually (asynchronously) enabled or stopped via the 2-wire i 2 c control interface. in this case all clocks are stopped in the low state. figure 1. pd# timing diagram power management timing when mode = 0, the device supports power management and pin 11 is input pd#. when mode = 1, this function is not available). a particular output is enabled only when both the i 2 c serial interface and this pin indicate that it should be enabled. the clocks may be disabled according to the following table in order to reduce the power consumption. all clocks are stopped in the low state. pci_f pd# pci (1:5) cpu (0:1) a b a: represents one pci clock wait cycle b: represents one cpu clock wait cycle all clocks maintain a valid high period on transitions from running to stopped. the cpu and pci clocks transition between running and stopped by waiting for one positive edge on pci_f followed by a negative edge on the clock of interest, after which high levels of the outputs are either enabled or disabled. see figure 1 below.
240 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 12345678901 2 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 ps8164b 03/15/99 pi6c104 spread spectrum clock synthesizer for desktop pentium ii s r e t e m a r a pn o i t p i r c s e ds n o i t i d n o c t s e t. n i m. p y t. x a ms t i n u i 2 d d t n e r r u c v 5 . 2 v 2 d d 0 = # d p , v 5 2 6 . 2 = . x a m = d a o l c 0 0 1 m a i 2 d d v 2 d d z h m 6 6 . 6 6 @ v 5 2 6 . 2 = . x a m = d a o l c 2 7 a m i 2 d d v 2 d d z h m 0 0 1 @ v 5 2 6 . 2 = . x a m = d a o l c 0 0 1 i d d t n e r r u c v 3 . 3 v d d 0 = # d p , v 5 6 4 . 3 = . x a m = d a o l c 0 0 5 m a i d d v d d z h m 6 6 . 6 6 @ v 5 6 4 . 3 = . x a m = d a o l c 0 7 1 a m i d d v d d z h m 0 0 1 @ v 5 6 4 . 3 = . x a m = d a o l c 0 7 1 storage temperature .............................................................. ?65c to +150c ambient temperature with power applied ............................... ?0c to +70c 3.3v supply voltage to ground potential .................................. ?0.5v to +4.6v 2.5v supply voltage to ground potential .................................. ?0.5v to +3.6v dc input voltage ....................................................................... ?0.5v to +4.6v dc electrical characteristics (v dd = +3.3v 5%, v dd2 = +2.5v 5%, t a = 0c to +70c) maximum ratings (above which the useful life may be impaired. for user guidelines, not tested.) note: stresses greater than those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability.
241 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 12345678901 2 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 ps8164b 03/15/99 pi6c104 spread spectrum clock synthesizer for desktop pentium ii dc operating specifications l o b m y ss r e t e m a r a ps n o i t i d n o c. n i m. x a ms t i n u v , e g a t l o v t u p n i d d % 5 v 3 . 3 = v 3 h i e g a t l o v h g i h t u p n iv e r o c d d 0 . 2v e r o c d d 3 . 0 + v v 3 l i e g a t l o v w o l t u p n iv s s 3 . 0 -8 . 0 i l i t n e r r u c e g a k a e l t u p n iv < 0 n i v < e r o c d d 5 -5 + m a v , e g a t l o v t u p t u o 2 d d 5 . 2 =% 5 v v h o e g a t l o v h g i h t u p t u oi h o a m 1 - =0 . 2 v v l o e g a t l o v w o l t u p t u oi l o a m 1 =4 . 0 v , e g a t l o v t u p t u o d d % 5 v 3 . 3 = v h o e g a t l o v h g i h t u p t u oi h o a m 1 - =4 . 2 v v l o e g a t l o v w o l t u p t u oi l o a m 1 =4 . 0 v , e g a t l o v t u p t u o d d 3 . 3 =% 5 v v h o p e g a t l o v h g i h t u p t u o s u b i c pi h o a m 1 - =4 . 2 v v l o p e g a t l o v w o l t u p t u o s u b i c pi l o a m 1 =5 5 . 0 c n i e c n a t i c a p a c n i p t u p n i5 f p c l a t x e c n a t i c a p a c s n i p l a t x5 . 3 10 . 8 15 . 2 2 c t u o e c n a t i c a p a c n i p t u p t u o6 l n i p e c n a t c u d n i n i p7h n t a e r u t a r e p m e t t n e i b m aw o l f r i a o n00 7c
242 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 12345678901 2 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 ps8164b 03/15/99 pi6c104 spread spectrum clock synthesizer for desktop pentium ii type 1: 2.5v clock buffers l o b m y ss r e t e m a r a ps n o i t i d n o c. n i m. p y t. x a ms t i n u i n i m h o t n e r r u c p u - l l u pv t u o v 0 . 1 =7 2 - a m i x a m h o t n e r r u c p u - l l u pv t u o v 5 7 3 . 2 =7 2 - i n i m l o t n e r r u c n w o d - l l u pv t u o v 2 . 1 =7 2 i x a m l o t n e r r u c n w o d - l l u pv t u o v 3 . 0 =0 3 t h r e t a r e g d e e s i r t u p t u o 1 e p y t v 5 . 2v 0 . 2 - v 4 . 0 @ % 5 v 5 . 214 s n / v t h f e t a r e g d e l l a f t u p t u o 1 e p y t v 5 . 2v 4 . 0 - v 0 . 2 @ % 5 v 5 . 214 buffer specifications v d d ) v ( e g n a r( e c n a d e p m i w )e p y t r e f f u b 5 2 6 . 2 - 5 7 3 . 25 4 - 5 . 3 11 e p y t 5 6 4 . 3 - 5 3 1 . 35 5 - 2 15 e p y t type 5: 3.3v clock buffers l o b m y ss r e t e m a r a ps n o i t i d n o c. n i m. p y t. x a ms t i n u i n i m h o t n e r r u c p u - l l u pv t u o v 0 . 1 =3 3 - a m i x a m h o t n e r r u c p u - l l u pv t u o v 5 3 1 . 3 =3 3 - i n i m l o t n e r r u c n w o d - l l u pv t u o v 5 9 . 1 =0 3 i x a m l o t n e r r u c n w o d - l l u pv t u o v 4 . 0 =8 3 t h r e t a r e g d e e s i r t u p t u o 5 e p y t v 3 . 3v 4 . 2 - v 4 . 0 @ % 5 v 3 . 314 s n / v t h f e t a r e g d e l l a f t u p t u o 5 e p y t v 3 . 3v 4 . 0 - v 4 . 2 @ % 5 v 3 . 314
243 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 12345678901 2 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 ps8164b 03/15/99 pi6c104 spread spectrum clock synthesizer for desktop pentium ii ac timing k c o l c t s o h . 1 e r u g i f t e s f f o k l c i c p o t s r e t e m a r a p z h m 6 6z h m 0 0 1 s t i n u . n i m. x a m. n i m. x a m t p k h ) v 5 . 2 (d o i r e p k l c t s o h0 . 5 15 . 5 10 . 0 15 . 0 1 s n t h k h ) v 5 . 2 (e m i t h g i h k l c t s o h2 . 50 . 3 t l k h ) v 5 . 2 (e m i t w o l k l c t s o h0 . 58 . 2 t e s i r h ) v 5 . 2 (e m i t e s i r k l c t s o h4 . 06 . 14 . 06 . 1 t l l a f h ) v 5 . 2 (e m i t l l a f k l c t s o h4 . 06 . 14 . 06 . 1 t r e t t i j ) v 5 . 2 (r e t t i j k l c t s o h0 5 20 5 2s p ) v 5 . 2 ( e l c y c y t u dv 5 2 . 1 t a d e r u s a e m5 45 55 45 5% t w k s h ) v 5 . 2 (w e k s k l c s u b t s o h5 7 15 7 1s p t l z p t , h z p y a l e d e l b a n e t u p t u o0 . 10 . 80 . 10 . 8 s n t z l p t , z h p y a l e d e l b a s i d t u p t u o0 . 10 . 80 . 10 . 8 t b t s h p u - r e w o p m o r f n o i t a z i l i b a t s k l c t s o h33s m t p k p d o i r e p k l c i c p0 . 0 3 0 . 0 3 s n t s p k p y t i l i b a t s d o i r e p k l c i c p0 0 50 0 5s p h k p t e m i t h g i h k l c i c p0 . 2 10 . 2 1 s n t l k p e m i t w o l k l c i c p0 . 2 10 . 2 1 t w k s p w e k s k l c s u b i c p0 0 50 0 5s p t t e s f f o p h t e s f f o k c o l c i c p o t t s o h5 . 10 . 45 . 10 . 4s n t b t s p p u - r e w o p m o r f n o i t a z i l i b a t s k l c i c p33s m
244 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 12345678901 2 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 ps8164b 03/15/99 pi6c104 spread spectrum clock synthesizer for desktop pentium ii output buffer test point 2.0 1.25 0.4 thkh duty cycle thkp 2.5v clocking interface thkl t hfall t hrise 2.4 1.5 0.4 tpkh tpkp 3.3v clocking interface (ttl) tpkl t pfall t prise test load figure 2. clock output waveforms figure 1. host clock and pci clk timing 1.25v 2.5v t hpoffset host clk pci clk v ss 1.5v 3.3v v ss t hpoffset 1.25v 2.5v host clk v ss t hskw pci clk 1.5v 3.3v v ss t pskw 1.5v 1.25v 1.25v
245 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 12345678901 2 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 ps8164b 03/15/99 pi6c104 spread spectrum clock synthesizer for desktop pentium ii pcb layout suggestion note: this is only a suggested layout. there may be alternate solutions depending on actual pcb design and layout. as a general rule, c2-c6 should be placed as close as possible to their respective v dd . recommended capacitor values: c2-c6 ............... 0. 1uf, ceramic c1, c7 ............. 22uf c2 c6 c5 c4 c3 fb2 vcc c7 22 m f via to vdd plane via to gnd plane void in power plane 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 vss vdd vdd vdd vdd vdd vss vss vss fb1 vcc c1 22 m f
246 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 12345678901 2 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 ps8164b 03/15/99 pi6c104 spread spectrum clock synthesizer for desktop pentium ii k c o l cd a o l . n i md a o l . x a ms t i n us e t o n ) k l c h ( s k c o l c u p c0 10 2 f p s d a o l 2 e l b i s s o p , d a o l e c i v e d 1 ) k l c p ( s k c o l c i c p0 30 3s t n e m e r i u q e r 1 . 2 i c p s t e e m z h m 8 4 , f e r0 10 2d a o l e c i v e d 1 minimum and maximum expected capacitive loads notes: 1. maximum rise/fall times are guaranteed at maximum specified load for each type of output buffer. 2. minimum rise/fall times are guaranteed at minimum specified load for each type of output buffer. 3. rise/fall times are specified with pure capacitive load as shown. testing is done with an additional 500 w resistor in parallel. design guidelines to reduce emi 1. place series resistors and ci capacitors as close as possible to the respective clock pins. typical value for ci is 10pf. r s series resistor value can be increased to reduce emi provided that the rise and fall time are still within the specified values. 2. minimize the number of ?vias? of the clock traces. 3. route clock traces over a continuous ground plane or over a continuous power plane. avoid routing clock traces from plane to plane (refer to rule #2). 4. position clock signals away from signals that go to any cables or any external connectors. cpuclk pciclk ref apic rs rs rs cl cl cl pi6c104 1 device load meets pci2.1 req. 1 device load 2 2 7 rs ct 1 device load
247 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 12345678901 2 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 ps8164b 03/15/99 pi6c104 spread spectrum clock synthesizer for desktop pentium ii pericom semiconductor corporation 2380 bering drive ? san jose, ca 95131 ? 1-800-435-2336 ? fax (408) 435-1100 ? http://www.pericom.com 28-pin ssop package data seating plane .050 bsc 1 0-8? .2914 .2992 x.xx x.xx denotes dimensions in millimeters 7.40 7.60 .6969 .7125 17.70 18.10 1.27 .0926 .1043 2.35 2.65 .394 .419 10.00 10.65 .0040 .0118 0.10 0.30 .013 .020 0.33 0.51 .010 .029 0.254 0.737 .0091 .0125 0.23 0.32 0.41 1.27 .016 .050 x 45? 28 .021 .031 0.533 0.787 ref 28-pin soic package data ordering information n / pn o i t p i r c s e d h 4 0 1 c 6 i pe g a k c a p p o s s n i p - 8 2 s 4 0 1 c 6 i pe g a k c a p c i o s n i p - 8 2 .390 .413 .078 .002 seating plane .0098 max. .0256 bsc .022 .037 .004 .009 .291 .322 1 28 .197 .220 0.25 x.xx x.xx denotes dimensions in millimeters 0.050 7.40 8.20 0.55 0.95 0.09 0.25 5.00 5.60 2.0 9.90 10.50 0.65 max min

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